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<div class="textblock"><pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who  Date     Changes
</p>
<hr/>
<p>
1.00a drg  01/19/00 First release
1.01a sdm  11/09/11 The <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> and <a class="el" href="struct_x_scu_gic___config.html" title="This typedef contains configuration information for the device. ">XScuGic_Config</a> structures have changed.
              The HandlerTable (of type XScuGic_VectorTableEntry) is
              moved to <a class="el" href="struct_x_scu_gic___config.html" title="This typedef contains configuration information for the device. ">XScuGic_Config</a> structure from <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> structure.</pre><pre>              The "Config" entry in <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> structure is made as
              pointer for better efficiency.</pre><pre>              A new file named as <a class="el" href="xscugic__hw_8c.html">xscugic_hw.c</a> is now added. It is
              to implement low level driver routines without using
              any xscugic instance pointer. They are useful when the
              user wants to use xscugic through device id or
              base address. The driver routines provided are explained
              below.
              XScuGic_DeviceInitialize that takes device id as
              argument and initializes the device (without calling
              XScuGic_CfgInitialize).
              XScuGic_DeviceInterruptHandler that takes device id
              as argument and calls appropriate handlers from the
              HandlerTable.
              XScuGic_RegisterHandler that registers a new handler
              by taking xscugic hardware base address as argument.
              LookupConfigByBaseAddress is used to return the
              corresponding config structure from XScuGic_ConfigTable
              based on the scugic base address passed.
1.02a sdm  12/20/11 Removed AckBeforeService from the <a class="el" href="struct_x_scu_gic___config.html" title="This typedef contains configuration information for the device. ">XScuGic_Config</a>
              structure.
1.03a srt  02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
              *_hw.h
              Added APIs</p>
<ul>
<li><a class="el" href="group__scugic__api.html#gac8e95bba26e2b07a882cb03750540b4d" title="Sets the interrupt priority and trigger type for the specificd IRQ source. ">XScuGic_SetPriTrigTypeByDistAddr()</a></li>
<li><a class="el" href="group__scugic__api.html#ga19437ca93adc808161232c5667d7ca62" title="Gets the interrupt priority and trigger type for the specificd IRQ source. ">XScuGic_GetPriTrigTypeByDistAddr()</a>
              (CR 702687)
                Added support to direct interrupts to the appropriate CPU. Earlier
                  interrupts were directed to CPU1 (hard coded). Now depending
                  upon the CPU selected by the user (xparameters.h), interrupts
                  will be directed to the relevant CPU. This fixes CR 699688.
1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
                  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
                  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
            XScuGic_GetPriTrigTypeByDistAddr to <a class="el" href="xscugic__hw_8c.html">xscugic_hw.c</a>.
                  This is fix for CR#705621.
1.05a hk   06/26/13 Modified tcl to export external interrupts correctly to
                    xparameters.h. Fix for CR's 690505, 708928 &amp; 719359.
2.0   adk  12/10/13 Updated as per the New Tcl API's
2.1   adk  25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
3.2   asa  02/29/16 Modified DistributorInit function for Zynq AMP case. The
                  distributor is left uninitialized for Zynq AMP. It is assumed
            that the distributor will be initialized by Linux master. However
            for CortexR5 case, the earlier code is left unchanged where the
            the interrupt processor target registers in the distributor is
            initialized with the corresponding CPU ID on which the application
            built over the scugic driver runs.
            These changes fix CR#937243.</li>
</ul>
</pre><pre>3.4   asa  04/07/16 Created a new static function DoDistributorInit to simplify
           the flow and avoid code duplication. Changes are made for
           USE_AMP use case for R5. In a scenario (in R5 split mode) when
           one R5 is operating with A53 in open amp config and other
           R5 running baremetal app, the existing code
           had the potential to stop the whole AMP solution to work (if
           for some reason the R5 running the baremetal app tasked to
           initialize the Distributor hangs or crashes before initializing).
           Changes are made so that the R5 under AMP first checks if
           the distributor is enabled or not and if not, it does the
           standard Distributor initialization.
           This fixes the CR#952962.
3.6   ms   01/23/17 Modified xil_printf statement in main function for all
                    examples to ensure that "Successfully ran" and "Failed"
                    strings are available in all examples. This is a fix
                    for CR-965028.
      kvn  02/17/17 Add support for changing GIC CPU master at run time.
      kvn  02/28/17 Make the CpuId as static variable and Added new
                    XScugiC_GetCpuId to access CpuId.
      ms   03/17/17 Added readme.txt file in examples folder for doxygen
                    generation.
3.7   ms   04/11/17 Modified tcl file to add suffix U for all macro
                    definitions of scugic in xparameters.h
3.8   mus  07/05/17 Updated scugic.tcl to add support for interrupts connected
                    through util_reduced_vector IP(OR gate)
      mus  07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize
                    the HandlerTable in XScuGic_ConfigTable to 0, it removes
                    the compilation warning in <a class="el" href="xscugic__g_8c.html">xscugic_g.c</a>. Fix for CR#978736.
      mus  07/25/17 Updated xdefine_gic_params proc to export correct canonical
                    definitions for pl to ps interrupts.Fix for CR#980534
3.9   mus  02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
                    XScuGic_InterruptUnmapFromCpu, These API's can be used
                    by applications to unmap specific/all interrupts from
                    target CPU.
3.10  aru  08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
4.0   mus  11/22/18 Fixed bugs in software interrupt generation through
                     XScuGic_SoftwareIntr API
4.1   asa  03/30/19 Made changes not to direct each interrupt to all
                    available CPUs by default. This was breaking AMP
                    behavior. Instead every time an interrupt enable
                    request is received, the interrupt was mapped to
                    the respective CPU. There were several other changes
                    made to implement this. This set of changes was to
                    fix CR-1024716.
4.1   mus  06/19/19 Added API's XScuGic_MarkCoreAsleep and
                    XScuGic_MarkCoreAwake to mark processor core as
                    asleep or awake. Fix for CR#1027220.
4.5   asa  03/07/21 Included a header file xil_spinlock.h to ensure that
                    GIC driver can use newly introduced spinlock
                    functionality.
4.6     sk   08/05/21 Fix scugic misrac violations.
4.7   dp   11/22/21 Added new API <a class="el" href="group__scugic__api.html#ga72b9aec992716861e5f0929e4d0d9f7c" title="Checks whether the XScGic is initialized or not given the device ID. ">XScuGic_IsInitialized()</a> to check and return
                    the GIC initialization status.
5.0   mus  22/02/22 Add support for VERSAL NET
        adk  04/18/22 Replace infinite while loops in the examples with
                      Xil_WaitForEventSet() API.
      dp   04/25/22 Correct Trigger index calculation in macro
                    XScuGic_Get_Rdist_Int_Trigger_Index
5.0   dp   11/07/22 Add macros for accessing the GIC Binary Point and
                    Running Priority registers of Cortex-R52.
5.1   mus  02/13/23 Updated XScuGic_CfgInitialize, XScuGic_Enable and
                    XScuGic_Disable to support interrupts on each core
                    of all CortexA78/CortexR52 clusters in VERSAL NET SoC.
                    While at it, modified interrupt routing logic to make
                    use of CPU affinity register instead of XPAR_CPU_ID macro.
                    Also, XScuGic_CfgInitialize has been updated to find
                    redistributor base address of core on which API is
                    executed, redistributor address will be stored in newly
                    added member of <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> data structure "RedistBaseAddr".
                    It fixes CR#1150432.
5.2   ml   03/02/23 Add description to fix Doxygen warnings.
5.2   adk  04/14/23 Added support for system device-tree flow.
5.5   ml   01/08/25 Update datatype of distributor and cpu base address in
                    scugic config structure.
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